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XE1205
5.2.3.2
Bit synchronizer in continuous mode
The raw output signal from the demodulator may contain jitter and glitches. The bit synchronizer converts the data output
of the demodulator into a glitch-free bit-stream DATA and generates a synchronized clock DCLK to be used for sampling
the DATA output (see below). DCLK is available on pin IRQ_1 when the chip operates in continuous mode.
DATA (NRZ)
DCLK
Figure 3: Bit synchronizer timing diagram
For proper operation, in addition to the requirement for the modulation index defined in Section 5.2.3.1, the Bit
Synchronizer must first receive three bytes of alternating logic value preamble, i.e. “0101” sequences. After this startup
phase, the rising edge of DCLK signal is centered on the demodulated bit. Subsequent data transitions will preserve this
centering.
This has two implications:
?
?
If the Bit Rates of Transmitter and Receiver are known to be the same, the XE1203F will be able to receive an
infinite unbalanced sequence (all “0s” or all ”1s”) with no restriction.
If there is a difference in Bit Rate between Tx and Rx, the amount of adjacent bits at the same level that the
BitSync can withstand can be estimated as:
Number of bits = 0.5 ?
BR
Δ BR
This implies approximately 6 consecutive unbalanced bytes when the Bit Rate precision is 1%, which is easily achievable
(crystal tolerance is in the range of 50 to 100 ppm). It is recommended that the bit rate accuracy be better than ±5% (3%
for Konnex mode operation).
The bit synchronizer is enabled by default. It is controlled by RXParam_Disable_bitsync. If the bit synchronizer is
disabled the output of the demodulator is directed to DATA and the DCLK output (IRQ_1 Pin in continuous mode) is set
to ‘0’.
The received bit rate is defined by the value of the MCParam_Br(6:0) configuration register, and is calculated as follows:
Bit rate =
152 . 34 e 3
int(Br(6 : 0)) + 1
where int(x) is the integer value of the unsigned binary representation of x.
For the Konnex standard operation, the bit rate is fixed at 32.768 kbit/s. The bit synchronizer is automatically configured
with the right bit rate value if the MCParam_Knx configuration bit is set high.
If needed, it is possible to select intermediate bit rates by changing the Over-Sampling Ratio (OSR) of the bit
synchronizer, whose default value is 32. The latter can be superseded by setting high the register TParam_Chg_OSR. In
this case, the bit rate becomes:
?
Bit rate =
152 . 34 e 3 32
int(Br(6 : 0)) + 1 int( OSR ( 7 : 0 )) + 1
,
? Semtech 2008
10
www.semtech.com
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